Technical Achievements

Uri Weiser - Emeritus Professor

Major Technical Achievements (my technical tombstone):

  • Analytical model of fast feedback amplifier with delay (1975, Master thesis)
  • Mathematical and graphical model of Systolic Arrays (1981, Ph.D thesis)
  • Initiation, definition and architecture simulator of Intel’s first Pentium Processor (1988)
  • Invention (with Alex Peleg) of the Trace cache (1989)
  • Performance analysis and potential of X86 Out of Order machine (with Peleg) (1990)
  • Leading the Intel’s MMX technology (1996)
  • Leading at Intel the Asymmetric Media Architecture Initiative (failed at Intel) (2002, confidential material)
  • Content Aware Action concept (with Horowitz, Ganor, Shachar, Cohen Commex-Technologies) (2007)
  • Nahalal – Cache organization for Chip MultiProcessor (with Guz, Keidar and Kolodny) (2008)
  • Multi-Core vs. Multi-Thread Machines (with Guz, Bolotin, Keidar, Mendelson and Kolodny) (2009)
  • MultiAmdahl Heterogeneous framework (with Tsahee Zidenberg, Isaac Kesslassy) (2010)
  • Pipelined MultiThreading – Memristor based pipelined microarchitecture (with Shahar Kvatinsky, Avinoam Kolodny) (2012)
  • Memory Intensive Architecture – Call for new compute structures in large-memory-environment (2013)
  • The Funnel structure – Big Data Read-Once case (Non-Temporal locality Memory Access) (2016)
    1. Bypass DRAM to save energy for Big Data Read-Once memory accesses ak’a usage of “Funnel for Read-Once Data” (2014)
      first exposure at Yale@75 conference – 9/2014 second at UCLA February 2015
    2. Big Data applications: We identified two memory access patterns: Temporal-Locality memory accesses (low storage BW requirement) – to be handle by current memory subsystem, while Read-Once memory accesses (High storage BW requirement) – to be handle as close as possible to the source (e.g. usage of Funnel function at SSD structure) (2015).
      Current memory subsystems support accessing temporal data (i.e. usage of DRAM and caches). Many Big Data applications are characterizes by heavy Read Once (e.g. Streaming) memory accesses.