Publications

Uri Weiser - Emeritus Professor

Books, reviewed professional journals, reviewed conferences, reports

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Theses

Books, reviewed professional journals, reviewed conferences, reports:

  • Kaplan, L. Yavitz, U. Weiser, R. Ginosar
    “An In-Storage Implementation of Smith-Waterman in Resistive CAM”
    In-Memory and In-Storage Computing with Emerging Technologies workshop (PACT-2016). Gold Medal in the 2016 ACM Student Research Competition, PACT 2016 Haifa Israel
  • Rotem, R. Ginosar, U. Weiser, A. Mendelson, E. Weissmann, Y. Aizik
    “H-EARtH: Heterogeneous Multi-Core Platform Energy Management”,
    Computer Journal, COMSI-2016-03-0107.R1 2016
  • Morad, N. Shalev, I. Keidar, A. Kolodny, U. Weiser
    “EFS: Energy-Friendly Scheduler for Memory Bandwidth Constrained Systems”,
    Journal of Parallel and Distributed Computing 2016
  • Morad, G. Shomron, M. Erez, A. Kolodny, U. Weiser,
    “Optimizing Read-Once Data Flow in Big-Data Applications”
    Computer Architecture Letters (CAL) Journal 2016
  • E. Rotem, R. Ginosar, A,. Mendelson, U. Weiser 
    “Power and Thermal Constraints of Modern System-On-a-Chip Computer”, Microelectronics Journal Volume 46, Issue 12, Part A, December 2015, Pages 1225–1229
  • L. Peled, S. Mannor, U. Weiser, Y. Etsion
    “Semantic Locality and Context based Prefetching Using Reinforcement Learnings”, ISCA-2015 Conference, Portland US, June 2015.
  • A. Fuchs, S. Mannor, U. Weiser, Y. Etsion
    “Loop-Aware Memory Prefetching Using Code Block Working Sets”, MICRO-47 Conference, Cambridge UK, December 2014.
  • S. Kvatinsky, A. Kolodny, E. Friedman, U. Weiser
    “MAGIC? Memristor Aided LoGIC”, IEEE Transactions on Circuits and Systems Journal, Vol. 61, November 2014.
  • S. Kvatinsky, N. Wald, G. Satat, E. G. Friedman, A. Kolodny, and U. Weiser
    “Memristor-Based Material Implication (IMPLY) Logic: Design Principles and Methodologies”, IEEE Transactions on Very Large Scale Integration (VLSI) Journal, Vol. 22, pp. 2054-2066, October 2014.
  • L. Azriel, A. Mendelson, U. Weiser
    “Peripheral Memory: a Technique for Fighting Memory Bandwidth Bottleneck”, Computer Architecture Letters (CAL) Journal, 2014.
  • S. Kvatinsky, D. Belousov, S Liman, G. Satat, N. Wald, E. Friedman, A. Kolodny, U. Weiser
    “MAGIC – memristor Aided LoGic” IEEE transaction on Circuits and Systems Journal, 2014.
  • T. Zidenberg, Isaac Keslassy, U. Weiser
    “Optimal Resource Allocation with MultiAmdahl” IEEE MICRO Journal, August 2013.
  • S. Kvatinsky, G. Satat, N. Wald, E. G. Friedman, A. Kolodny, U. Weiser
    “Memristor-based Material Implication (IMPLY) Logic: Design Principles and Methodologies” submitted to IEEE Transaction on Very Large Scale Integration (VLSI) Systems Journal, 2013.
  • S. Kvatinsky, Y. Nacson, Y. Etsion, E. Friedman, A. Kolodny, U. Weiser
    Memristor-Based Multithreading” Computer Architecture Letters (CAL) Journal, March 2013.
  • S. Kvatinsky, K. Talisveyberg, D. Fliter, E. G. Friedman, A. Kolodny and U. Weiser
    Models of Memristors for SPICE Simulations” Proceedings of the IEEE Convention of Electrical and Electronics Engineers in Israel, pp. 1-5, November 2012.
  • Amir Morad, Tomer Y. Morad, Leonid Yavits, Ran Ginosar, U. Weiser
    “Generalized MultiAmdahl: Optimization of Heterogeneous Multi-Accelerator SoC”, Technion CCIT Technical Report #812, September 2012; also at Computer Architecture Letters, November 2012.
  • S. Kvatinsky, E. G. Friedman, A. Kolodny and U. Weiser
    TEAM: ThrEshold Adaptive Memristor Model“, IEEE Transactions on Circuits and Systems, Journal Vol. 60, No. 1, pp. 211-221, January 2013. Best paper award
  • T. Morad, A. Kolodny, U. Weiser
    Task Scheduling Based On Thread Essence and Resource Limitations“, Journal of Computers, vol. 7, no. 1 (2012), 53-64, January 2012.
  • S. Kvatinsky, K. Talisveyberg, D. Fliter, E.G. Friedman, A. Kolodny and U.C. Weiser
    “Verilog-A for Memristor Models”, Technion CCIT Technical Report #801, January 2012.
  • T. Zidenberg, Isaac Keslassy, U. Weiser
    MultiAmdahl: How Should I Divide My Heterogeneous Chip?“, Computer Architecture Letters (CAL), February 20, 2012. CAL best paper award
  • E. Rotem, R. Ginosar, A. Mendelson, U. Weiser
    “EARtH – Energy Aware Race to Halt Finding the Operating Point of Minimal Platform Energy”, to be published in MICRO 2013.
  • S. Kvatinsky, E. Friedman, A. Kolodny, U. Weiser
    “Memristor-based IMPLY Logic Design Flow”, ICCD, pp. 142-147, October 2011.
  • T. Morad, A. Kolodny, U. Weiser
    “Scheduling Multiple Multithreaded Applications on Asymmetric and Symmetric Chip Multiprocessors”, PAAD’10, Conference, Dalian, LiaoNing, China, December 2010.
  • Z. Guz, O. Itzhak, I. Keidar, A. Kolodny, A. Mendelson, U. Weiser
    Threads vs. Caches: Modeling the Behavior of Parallel Workloads on High-Performance Engines“, Conference ICCD, Amsterdam, Holland, October 2010.
  • E. Rotem, R. Genosar, A. Medelson, U. Weiser
    “Multiple Clock and Voltage Domains for Chip Multi Processors” MICRO 2009 conference, NY, NY December 12th 2009. HiPeach grant award
  • A. Berman, U. Weiser
    Reliable Architecture for Flash Memory“, Workshop on Emerging Memory Technologies (WEMT) 2009 held in conjunction with ISCA-36 Austin, Texas, June 2009.
  • Z. Guz, E. Bolotin, I. Keidar, A. Kolodny, A. Mendelson, U. Weiser
    Multi-Core vs. Multi-thread Machines: Stay away from the valley” IEEE Computer Architecture Letters Journal, IEEE Publication, April 2009.
  • T. Morad, A. Kolodny, U. Weiser
    Multiple Multithreaded Applications on Asymmetric and Symmetric Chip MultiProcessors” CCIT (EE Technion) technical report #701, August 2008.
  • Z. Guz, I. Keidar, A. Kolodny, U. Weiser
    Utilizing Shared Data in Chip Multiprocessors with the Nahalal Architecture” SPAA, 20th ACM Symposium on Parallelism in Algorithms and Architectures, Munich, Germany, June 14-16, 2008. Won SPAA 2008 Conference’s best paper award
  • A. Elyada, R. Ginosar, U. Weiser
    Low-Complexity Policies for Energy-Performance Tradeoff” IEEE Transactions on Very Large Scale Integration Systems Journal to be published July 2008.
  • Z. Guz, I. Keidar, A. Kolodny, U. Weiser
    Nahalal: Cache Organization for Chip Multiprocessors” IEEE Computer Architecture Letters Journal, IEEE Publication, June 2007 also Technion Technical Report: CCIT 600, September 2006.
  • T. Morad, U. Weiser, A. Kolodny, M. Valero, E. Ayguade
    Performance, Power Efficiency and Scalability of Asymmetric Cluster Chip MultiProcessors” Computer Architecture Letter Journal, IEEE Publication, July 2005.
  • T. Morad, U. Weiser, A. Kolodny
    Why NOT Data Trace Cache”, WDDD 2005, Fourth Annual Workshop on Duplicating, Deconstructing and Debunking (Held in conjunction with ISCA32), Madison Wisconsin, June 4th, 2005.
  • T. Morad, U. Weiser, A. Kolodny
    ACCMP – Asymmetric Cluster Chip Multiprocessing”, EE Technion, Technical Report CCIT Report #488, June 2004.
  • N. Magen, A. Kolodny, U. Weiser, N. Shamir
    Interconnect – Power Dissipation in a Microprocessor”, IEEE SLIP2004 (System Level Interconnect Predication) Conference, Paris, February 2004.
  • M. Bekerman, S. Jourdan, R. Ronen, G. Kirshenboim, L. Rappoport, A. Yoaz, U. Weiser
    “Correlated Load – Address Predictors”, ISCA-26 Conference, Atlanta, May 1999.
  • U. Weiser et al
    “The Complete Guide to MMXTM Technology”, McGraw-Hill Book, (313 pages book, 9 authors), June 1997.
  • M. Mittal, A. Peleg, U. Weiser
    MMX Technology Architecture Overview“, Intel Technology Journal, September 1997.
  • A. Peleg , S. Wilkie, U. Weiser
    “Intel MMX for Multimedia PCs”, Communication of the ACM Journal, Vol 40, Number 1, p25-38, January 1997.
  • A. Peleg, U. Weiser
    “MMX Technology Extension to Intel Architecture”, IEEEMicro Journal, pp. 42-50, August 1996.
  • A. Peleg, U. Weiser, et al
    “The MMX Technology Extension to the Intel Architecture”, Intel Design Technology Conference (DTTC), Tucson, Arizona, June 1996.
  • U. Weiser, et al
    “Intel’s Multimedia Architecture Extension”, The 19th Convention of Electrical and Electronics Engineering in Israel, Jerusalem, Israel, November 5, 1996.
  • A. Peleg, U. Weiser
    “Dynamic Flow Instruction Cache Memory Organized Around Trace Segments Independent of Virtual Address Line”, United States Patent No. 5,381,533, Jan 10, 1995 (aka Trace Cache Patent (also in the patent list)
  • F. Klass, U. Weiser
    “Efficient Systolic Array for Matrix Multiplication“, proceedings of 1991 International Conference on Parallel Processing”, (ICPP) Boca Raton, FL, August 1991.
  • A. Peleg, U. Weiser
    “Future Trends in MicroProcessors: Out of Order Execution, Speculative Branching and their CISC Performance Potential”, proceedings of IEEE Conference, Tel-Aviv, Israel, March 1991.
  • U. Weiser, Y Yaari, A. Golbert, S. Rotem et al
    “Intel’s Px next generation Microprocessor” Intel internal confidential document (the initial definition of the Pentium Processor), January 1991.
  • U. Weiser, Y. Yaari
    “CISC Superscalar Processor”, Intel Design Technology Conference, Gleneden Beach, Oregon, June 1990.
  • U. Weiser, D. Perlmutter, Y. Yaari
    “Reducing the Cost of Branches for CISC MicroProcessors”, Intel Design Technology Conference, June 1989.
  • D. Alpert, D. Biran, L. Epstein, J. Levy, B. Maytal, Y. Sidi, U. Weiser
    “Trends in VLSI Microcomputer Design”, proceedings of International Conference on Computer Technology, System and Application (CompEuro-87), pp. 564-567, May 1987.
  • U. Weiser, Y. Sidi, L. Epstein, D. Biran, A. Kaminker
    “Design of the NS32532 MicroProcessor”, 1987 IEEE International Conference on Computer Design (ICCD): VLSI in computers and Processors, pp. 177-180, October 1987.
  • Y. Sidi, D. Alpert, D. Biran, L. Epstein, J. Levy, B. Maytal, U. Weiser
    “Design Consideration of an Advanced 32-bit MicroProcessor”, proceedings of IEEE Conference, TA, Israel, April 1987.
  • Y. Rimoni, I. Zisman, R. Genosar, U. Weiser
    “Communication Element for the Versatile MultiComputer”, proceedings of IEEE Conference, TA, Israel, April 1987.
  • U. Weiser, A.L. Davis
    “Wavefront Notation Tool for VLSI Array Design”, in VLSI System and Computation, H.T. Kung, R.F. Sproull, G.T. Steele Book Editors, Computer Science Press Inc., pp. 226-234, 1981.
  • L. Johnson, U. Weiser, D. Cohen, A.L. Davis
    Towards a Formal Treatment of VLSI Arrays“, proceedings of Caltech Conference on VLSI, January 1981.
  • U. Weiser, A. L. Davis
    Mathematical Representation for VLSI Arrays“, Univ. of Utah Tech. Report, UUCS-80-111, Sept. 1980.
  • U. Weiser, A. F. Arbel, A. Adin
    Speed Limitation of Feedback Amplifiers due to Signal Delay“, International Journal of Electronics Journal, Vol. 41, September 1975.
  • U. Weiser, A. F. Arbel, A. Adin
    “Analysis of Feedback Amplifiers considering the Amplifier Delay”, proceedings of IEEE Conference, Tel-Aviv, Israel, April 1975.

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Theses:

  • U. C. Weiser
    “Mathematical and Graphical Tool for the Creation of Computational Arrays”, Ph.D Thesis, August 1981, University of Utah, SLC, UT
  • U. C. Weiser
    “A Logarithmic Preamplifier for Laser Signal Detecting”, M.Sc Thesis, March 1975, Technion IIT, Haifa, Israel.