Patents & Awards

Uri Weiser - Emeritus Professor
  • IEEE/ACM Eckert Mauchly Award, 2016, awarded at ISCA 2016, Seoul South Korea June, 2016
    “For leadership and pioneering industry and academic work in high performance processors and multimedia architectures”
  • Global Industry Leader Award 2016
    “For your major impact on the development of Intel’s Pentium architecture and Intel’s MMX technology, for inventing the Trace Cache, and for being a role model for an entire generation of young engineers”. ChipEx 2016 Tel Aviv Israel May, 2016
  • S. Kvatinsky, E. Friedman, A. Kolodny, U. Weiser – Uzi and Michal Halevy Technion’s Innovative Applied Engineering Awards, June 2014
  • U. Weiser, E. Friedman, A. Kolodny, S. Kvatinsky – Hershel Rich Technion Innovation Award 2014
  • S. Kvatinsky, E. Friedman, A. Kolodny, U. Weiser “Memristor based Multithreading” US patent filed, number (14/219,0930), June 2013
  • Sanford Kaplan Prize 2013, “For Creative Management in High Tech in the 21st Century” – 1st place
  • Y. Peleg, T. Horowitz, U. Weiser; “Data path topology optimizations in computer systems”, US Patent Provisions, May 2009
  • Y. Cohen, U. Weiser et al; “System and Method for Routing Packets Using Tags”, US Patent Applications, May 2008, Serial No: 12/120,656
  • U. Weiser, et al; “System and Methods for Efficient Handling of Data Traffic and Processing within a Processing Device”, U.S. Patent Application July 2007, Serial No: 11/776,285, aka Content Aware Routing (Actions)
  • U. Weiser, et al; “A Mechanism for Enabling the Utilization of Idle OS Processors’ Cycles”, United States Patent in filing, September 2005
  • U. Weiser, et al; “Branch Prediction and Resolution Apparatus for Superscalar Computer Processor”, United States Patent No. 5,606,676, Feb. 25, 1997
  • U. Weiser, et al; “Boundary Markers for Indicating the Boundary of Variable Length Instruction to Facilitate Parallel Processing of Sequential Instructions”, United States Patent No. 5,450,605, Sep. 12, 1995
  • A. Peleg, U. Weiser; “Dynamic Flow Instruction Cache Memory Organized Around Trace Segments Independent of Virtual Address Line”, United States Patent No. 5,381,533, Jan 10, 1995, aka Trace Cache
  • U. Weiser, et al; “Branch Prediction and Resolution Apparatus for Superscalar Computer Processor”, United States Patent No. 5,442,756, Aug. 15, 1995
  • U. Weiser, D. Perlmutter, Y. Yaari; “Pipeline System for Executing Predicted Branch Target Instruction in a Cycle Concurrently with Execution of Branch Instruction”, United States Patent No. 5,265,213, Nov. 23, 1993
  • Intel Achievement Award (IAA) 1997, “For Innovation that Transformed MMX Technology from Concept to Reality”
  • Intel Achievement Award (IAA) 1990, “For the Initiation and Development of an X86 Performance Simulator” (the Pentium Processor simulator)
  • Intel Israel Design Center, Divisional Recognition Award (IDA) 1989, “In Recognition for Your Outstanding Achievement in Reviving the X86 Architecture by Generating the Px Product Proposal” (the initial definition of the Pentium Processor)

technical achievements